How is a processor built is what was answered through this project, at least a baseline RISC 5-stage no pipeline processor.
This was a course project under Prof. Urbi Chatterjee. We had to implement a processor with a data cache, using a reduced set architecture, in Verilog. I became quite proficient in iVerilog after this. To add a cherry on top, I implemented an assembler that converts MIPS assembly directly to 32 bit instruction set, that can then be picked up by the processor. The whole experience was added to my goal of understanding computers bottoms-up.
project
iitk
comp-arch
simulation